1·The interrupt controller hardware sends interrupts to any CPU.
中断控制器硬件可以将中断发送到任何CPU。
2·The essential hardwares of computer contain CPU, memory, interrupt controller, DMA controller, etc.
计算机硬件的核心器件有CPU、内存、中断控制器、DMA控制器，等等。
3·Typically what is enumerated is the number of input pins on all of the interrupt controller in the system.
一般来说是系统中断控制器上的所有输入引脚的个数。
4·The interrupt controller hardware needs to recognize the source of the interrupt and which partition should receive that interrupt.
中断控制器硬件需要确定中断源，以及应该接收该中断的分区。
5·In particular, the Cell processor includes an interrupt controller and an IOMMU implementation, both of which are incompatible with those supported by older kernel versions.
具体来说，Cell处理器包括一个中断控制器和一个IOMMU的实现，它们与早期的内核版本的支持都是不兼容的。
6·It is mainly composed of DMA controller (82c37), interrupt controller (82c59), programmable interval timers (82c54), DRAM refresh control, wait state generator and system reset logic.
其内部主要由DMA控制器(82c37)、中断控制器(82c59)、可编程间隔计时器(82c54)，DRAM刷新控制器，等待状态产生器，系统重置电路组成。
7·The role of the device driver, then, is to query the touch screen controller whenever an interrupt occurs, and to ask the controller to send the coordinates of the touch.
然后，这个设备驱动程序的角色是每当出现中断时就查询触摸屏控制器，并请求控制器发送触摸的坐标。
8·The host controller will automatically post an interrupt at a specified interval.
主控器会以特定的间隔自动发出一个中断。
9·PL/M-96 program language is used as the software of the controller. The signal frequencies are distinguished and the persistence time of the frequency is accumulated with interrupt process routine.
数字化控制器控制软件采用PL/M-96高级语言编程，其中断处理程序用于辩别信号频率、累计每一频率持续时间。
10·It is a high performance digital controller, which possesses a high resolution digital trigger, high precision synchronous interrupt pulses, and a high precision fast A/D converter.
系统内设计了高分辨率的数字触发器和高精度的同步中断脉冲以及高精度快速的A/D转换，实现了数字化高性能调节控制系统。